Memory device technology that three-dimensionally arranges memory cells has been discussed in, for example, JP-A 2007-266143. The memory device technology includes making memory holes in a stacked body in which a conductive layer, which functions as a control gate, and an insulating layer are multiply stacked alternately. A charge storage film is formed on the inner walls of the memory holes, and silicon is subsequently provided in the memory holes.
By repeating processes to alternately etch the conductive layers and the insulating layers, or collectively etching the conductive layers and the insulating layers at the same process, the memory holes are made in the stacked body thereof. Considering the productivity and the like during such etching, it is desirable to use an appropriate etching mask material which can be common to both the insulating layer and the conductive layer.